Interest has revived in MRAM magnetic memories with the development of magnetic tunnel junctions (MTJ) having a resistance compatible with the use of CMOS components and a high magnetoresistance at ambient temperature.
Such magnetic memories with magnetic tunnel junctions have been described for example in document U.S. Pat. No. 5,640,343. In their simplest forms, they comprise two magnetic layers having different coercivities, separated by a thin insulating layer. When the magnetizations of the respective storage and reference layers, constituting the two abovementioned magnetic layers located on either side of the tunnel barrier, are antiparallel, the resistance of the magnetic tunnel junction is high. Conversely, when the magnetizations are parallel, this resistance becomes low.
Preferably, these two magnetic layers are made from 3d metals (Fe, Co, Ni) and alloys thereof (possibly containing boron and zirconium so as to make the structure of said layers amorphous and to flatten their interfaces) and the insulating layers are conventionally made from amorphous alumina (AlOx) or crystalline magnesium oxide (MgO). Advantageously, the reference layer also called “pinned layer”, may itself consist of a stack of several layers, such as described for example in document U.S. Pat. No. 5,583,725, so as to constitute a layer known as a “synthetic antiferromagnetic (SAF)” layer. Similarly, for each of the memory points, it is possible to replace the single magnetic tunnel junction by a double magnetic tunnel junction, such as described for example in the publication Y. SAITO & al, Journal of Magnetism and Magnetic Materials>>, Volume 223, 2001, page 293. In this case, the storage layer is inserted between two insulating layers, the structure comprising two reference layers positioned on the sides opposite said respective insulating layers.
The most conventional architecture, known as Field Induced Magnetic Switching (FIMS), that is the reversal of the magnetization by an induced magnetic field, is that described in document U.S. Pat. No. 6,021,065 and in the publication “Journal of Applied Physics” vol. 81, 1997, page 3758 and shown in FIG. 1.
As may be observed in FIG. 1 illustrating the prior art, each memory element or memory point 10 consists of the combination of a CMOS technology transistor 12 and a magnetic tunnel junction MTJ 11. Said tunnel junction 11 comprises at least one magnetic layer 20, called “storage layer” or “free layer”, a thin insulating layer 21, and a magnetic layer 22 called “pinned layer”, also known as reference layer. The functioning of these magnetic memories with memory points, each consisting of a magnetic tunnel junction, consists, for writing, in generating a pulsed magnetic field created by the current lines or conductors associated with each of said magnetic points.
Thus, and in the context of the FIMS architecture, three levels of current lines are observed. In FIG. 1, the two levels of line 14 (word line) and 15 (bit line), generally positioned at 90° from one another, are designed to generate magnetic field pulses for switching the magnetization of the free layer 20 during the write process. These magnetic field pulses are produced by circulating in the current lines 14 and 15, short electric pulses, typically for 2 to 5 nanoseconds, and having a current of about several milliamperes. The strength of these pulses and their synchronization are adjusted, so that only the magnetization of the memory point located at the intersection of these two current lines is subject to switching.
An additional current line 16 level, also called “control line” is designed to control the opening and closing of the transistor selection or switching channel 12 associated with each memory point, in order to address each memory element individually. In other words, the CMOS transistors 12 are used as switches.
In write mode of the addressed memory point, the transistor 12 selected is in blocked or “OFF” mode, so that no current passes through the transistor. A current pulse I is sent into the two current lines 14 and 15 corresponding to the memory point 10 selected. The pulse amplitude of current I is such that the magnetic field created is insufficient to switch the memory points on the lines 14 or 15, except at the intersection of the lines 14 and 15 where the joint contribution of the two lines is sufficient to generate a magnetic field that is also sufficient, and capable of switching the magnetization of the layer 20 of the addressed memory point.
In read mode, the transistor 12 is in saturated or “ON” mode by applying a voltage onto the grid of said transistor through the control line 16. A testing current is then sent into the current line 14 which can only cross the memory point of which the transistor 12 is placed in saturated or “ON” mode. This current is used to measure the resistance of the magnetic tunnel junction 11 of said selected memory point 10. From the value of this resistance, the corresponding status of the memory point 10 is determined as “0” (for a low resistance parallel magnetization configuration) or “1” (for a high resistance antiparallel magnetization configuration).
It will have been understood from the above that the strength of the pulses passing through the current lines 14 and 15 and their synchronization are adjusted so that only the magnetization of the memory point located at the intersection of these two current lines (selected point) can switch under the effect of the magnetic field generated by the two conductors. The other memory points located on the same line or on the same column (half-selected points) are accordingly subjected only to the magnetic field of one of the conductors 14, 15, and are consequently not switched.
Due to the write mechanism of these memory points, it is possible to understand the limits of this architecture.
Insofar as the writing is provided by an external magnetic field, it is subject to the value of the individual switching field of each memory point. Since the switching field distribution function for all the memory points is wide (in fact, this distribution is wide due to the manufacturing imperfections, particularly associated with the etching of the memory points and the intrinsic statistical fluctuations associated with the thermally activated magnetization fluctuations), it is necessary for the magnetic field on the selected memory point to be higher than the highest switching field of the distribution, at the risk of accidentally switching certain memory points located on the line or on the corresponding column, where the switching field located in the lower part of the distribution is lower than the magnetic field generated by the line or column alone. Furthermore, the power consumption of the memory making use of such an external magnetic field is commensurately higher with a wider switching field distribution.
Moreover, whereas in general, the mean value of the switching field increases as the size of the memory points decreases, which is a desirable arrangement for reasons of space, a commensurately higher current is anticipated in the future product generations. In consequence, the electric power required for the functioning of these memories will be commensurately higher as the integration density increases.
Another drawback of these prior art memories concerns the stability of the magnetization of the free layer with regard to thermal fluctuations as the size of the memory point decreases. Indeed, the energy barrier to be crossed to switch the magnetization of this layer from one orientation to the other is proportional to the volume of said layer. As the volume decreases, the height of the barrier becomes comparable to the thermal agitation. The data written in the memory is then no longer preserved. To overcome this difficulty, it is necessary to increase the magnetic anisotropy of the free layer by selecting a material having a higher anisotropy or by accentuating the shape anisotropy of the memory point, for example. In doing so, however, the magnetic field required for magnetic switching increases, due to a higher power consumption to generate the field necessary for the magnetic switching. The electric current in the “word line” and in the “bit line” may even, in certain cases, exceed the limit threshold imposed by the electromigration in the conducting lines (typically about 107 A/cm2).